Apple Inc. is seeking a DV engineer to ensure bug-free first silicon for IP designs in Melbourne, Australia. The role requires developing test plans, building verification environments, and using advanced methodologies for quality assurance. Candidates should hold a Bachelor's degree and have strong knowledge of SystemVerilog, UVM, and verification methodologies. Preferred qualifications include experience in OOP, scripting languages, and verification tools. Apple promotes diversity and inclusion within its workforce.#J-18808-Ljbffr
Senior Design Verification Engineer - Systemverilog/Uvm
APPLE INC.
city of melbourne, city of melbourne
Published 4 days ago
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